Flash memories and ferroelectric memories are well-known as nonvolatile memories capable of retaining stored information even after a power supply is turned off.
Of these, the flash memories include a floating gate that is embedded in a gate insulating film of an insulated gate field effect transistor (IGFET). The flash memories store information by accumulating, in this floating gate, electric charges indicating the information to be stored. However, it is required for such flash memories that a tunnel current be applied to the gate insulating film at the time of writing and erasing the information. Thus, there is a drawback that the flash memories require relatively high voltage.
On the other hand, the ferroelectric memories, which are also referred to as ferroelectric random access memories (FeRAMs), store information by utilizing the hysteresis characteristic of a ferroelectric film provided in a ferroelectric capacitor. The ferroelectric film causes polarization in response to the voltage applied between upper and lower electrodes of the capacitor, and spontaneous polarization remains even after the voltage is turned off. When the polarity of the applied voltage is reversed, the spontaneous polarization is also reversed. Directions of the spontaneous polarization are associated with “1” and “0”, so that the information is written in the ferroelectric film. The voltage required for the FeRAMs to carry out writing is lower than that for the flash memories. In addition, there is also an advantage in that the FeRAMs are capable of writing at a higher rate than the flash memories. Furthermore, the FeRAM is also advantageous because high integration and high durability can be achieved.
In a ferroelectric capacitor provided to a FeRAM, a material used for the ferroelectric film of the capacitor is a ferroelectric oxide with a perovskite structure, such as a PZT(Pb(Zr, Ti) O3) film or SBT(SrBi2Ta2O9), and the amount of residual polarization charge of these ferroelectric oxides are as high as approximately 10 μC/cm2 to 30 μC/cm2.
When the ferroelectric oxide is exposed to reducing materials, such as hydrogen or moisture, oxygen in the film is reduced to cause the shortage of oxygen. Thus, the crystallinity of the ferroelectric oxide is deteriorated, and the ferroelectric characteristic of the ferroelectric capacitor, such as the amount of residual polarization charge, is deteriorated.
In the processes of manufacturing a semiconductor device such as a FeRAM, a required circuit is formed on the semiconductor substrate, and thereafter the semiconductor substrate is subjected to dicing, so that semiconductor chips are separated. At this time, the cross-section of the interlayer insulating film is exposed to the dicing surface of the semiconductor chip, and moisture in the external atmosphere enters the semiconductor chip from the cross-section. Consequently, the ferroelectric capacitor is caused to be easily deteriorated by the moisture.
For this reason, to provide a FeRAM with high quality, it is important that reducing materials entering the semiconductor chip from the outside after dicing are effectively blocked in order not to allow the reducing materials to deteriorate the ferroelectric capacitor.
As a structure to increase moisture resistance of the semiconductor chip after dicing, there is known a so-called seal ring. The seal ring is a ring-like structure that surrounds the circuits and bonding pads in the circumference of the semiconductor chip, and functions to block moisture from the outside.
One example of such seal rings is disclosed in Japanese Patent Application Publications No. 2004-297022 (patent literature 1) and No. 2005-175204 (patent literature 2).
Incidentally, in the processes of manufacturing the semiconductor device, a test probe is brought into contact with the bonding pad to test electric characteristics in a wafer state before the semiconductor substrate is subjected to dicing to be cut into semiconductor chips.
The seal ring disclosed in the patent literatures 1 and 2 has an effect of blocking moisture to some extent. However, it is likely that damages and cracks of the bonding pad would be caused by the test probe. Thus, it is likely that a penetration path of moisture, which extends from the circumference of the bonding pad to the ferroelectric capacitor, would be formed during testing electric characteristics at a wafer level. In addition, there also causes a disadvantage that a bonding wire, such as a gold wire, is easily separated from the bonding pad due to the damages of the bonding pad.
In light of the foregoing problem, in Japanese Unexamined Patent Application Publication No. Sho 60-241229 (patent literature 3), Hei 2-235356 (patent literature 4), and No. Hei 5-299484 (patent literature 5), and Japanese Patent Application Publications No. Hei 9-330963 (patent literature 6), a test pad and a bonding pad are formed separately. Then, during the test at a wafer level, the probe is brought into contact with only the test pad, so that damages would not be caused in the bonding pad during the test.
However, in the patent literatures 3 to 6, improvement of moisture resistance of the semiconductor chip is not considered at all.
In addition to the above-described patent literatures 1 to 6, a technique relating to the present application is also disclosed in Japanese Patent Application Publication No. 2004-296775, Japanese Patent No. 2917362, and Japanese Patent Application Publication No. 2003-92353.